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low skew, 1-to-16 differential-to-lvds clock distribution chip ICS8516 datasheet 8516 revision b 6/11/15 1 ?2015 integrated device technology, inc. g eneral d escription the ICS8516 is a low skew, high performance 1-to-16 differential- to-lvds clock distribution chip. the ICS8516 clk, nclk pair can accept any differential input levels and translates them to 3.3v lvds output levels. utilizing low voltage differential signaling (lvds), the ICS8516 provides a low power, low noise, point-to-point solution for distributing clock signals over controlled impedances of 100 . dual output enable inputs allow the ICS8516 to be used in a 1-to-16 or 1-to-8 input/output mode. guaranteed output and part-to-part skew speci cations make the ICS8516 ideal for those applications demanding well de ned performance and repeatability. b lock d iagram p in a ssignment f eatures ? sixteen differential lvds outputs ? clk, nclk pair can accept the following differential input levels: lvpecl, lvds, lvhstl, hcsl, sstl ? maximum output frequency: 700mhz ? translates any differential input signal (lvpecl, lvhstl, sstl, dcm) to lvds levels without external bias networks ? translates any single-ended input signal to lvds with resistor bias on nclk input ? multiple output enable inputs for disabling unused outputs in reduced fanout applications ? lvds compatible ? output skew: 90ps (maximum) ? part-to-part skew: 500ps (maximum) ? propagation delay: 2.4ns (maximum) ? additive phase jitter, rms: 148fs (typical) ? 3.3v operating supply ? 0? to 70? ambient operating temperature ? available in lead-free rohs compliant package 48-lead lqfp 7mm x 7mm x 1.4mm body package y package top view
low skew, 1-to-16 differential-to-lvds clock distribution chip 8516 data sheet 2 revision b 6/11/15 t able 1. p in d escriptions number name type description 1, 6, 12, 25, 31, 36 v dd power positive supply pins. 2, 3 nq5, q5 output differential output pair. lvds interface levels. 4, 5 nq4, q4 output differential output pair. lvds interface levels. 7, 17, 20, 30, 41, 44 gnd power power supply ground. 8, 9 nq3, q3 output differential output pair. lvds interface levels. 10, 11 nq2, q2 output differential output pair. lvds interface levels. 13, 14 nq1, q1 output differential output pair. lvds interface levels. 15, 16 nq0, q0 output differential output pair. lvds interface levels. 18 nclk input pullup inverting differential clock input. 19 clk input pulldown non-inverting differential clock input. 21, 22 q15, nq15 output differential output pair. lvds interface levels. 23, 24 q14, nq14 output differential output pair. lvds interface levels. 26, 27 q13, nq13 output differential output pair. lvds interface levels. 28, 29 q12, nq12 output differential output pair. lvds interface levels. 32, 33 q11, nq11 output differential output pair. lvds interface levels. 34, 35 q10, nq10 output differential output pair. lvds interface levels. 37, 38 q9, nq9 output differential output pair. lvds interface levels. 39, 40 q8, nq8 output differential output pair. lvds interface levels. 42, 43 oe2, oe1 input pullup output enable. oe2 controls outputs q8, nq8 thru q15, nq15; oe1 controls outputs q0, nq0 thru q7, nq7. lvcmos/lvttl interface levels. 45, 46 nq7, q7 output differential output pair. lvds interface levels. 47, 48 nq6, q6 output differential output pair. lvds interface levels. note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values.
revision b 6/11/15 8516 data sheet 3 low skew, 1-to-16 differential-to-lvds clock distribution chip t able 2. p in c haracteristics t able 3a. c ontrol i nput f unction t able t able 3b. c lock i nput f unction t able inputs outputs oe1 oe2 q0:q7 nq0:nq7 q8:q15 nq8:nq15 0 0 hi z hi z hi z hi z 1 0 active active hi z hi z 0 1 hi z hi z active active 1 1 active active active active in the active mode, the state of the outputs are a function of the clk and nclk inputs as described in table 3b. inputs outputs input to output mode polarity clk nclk q0:q15 nq0:nq15 0 1 low high differential to differential non inverting 1 0 high low differential to differential non inverting 0 biased; note 1 low high single ended to differential non inverting 1 biased; note 1 high low single ended to differential non inverting biased; note 1 0 high low single ended to differential inverting biased; note 1 1 low high single ended to differential inverting note 1: please refer to the application information section, ?iring the differential input to accept single ended levels? symbol parameter test conditions minimum typical maximum units c in input capacitance 4 pf r pullup input pullup resistor 51 k r pulldown input pulldown resistor 51 k c pd power dissipation capacitance (per output) 4pf
low skew, 1-to-16 differential-to-lvds clock distribution chip 8516 data sheet 4 revision b 6/11/15 t able 4a. p ower s upply dc c haracteristics , v dd = 3.3v?%, t a = 0? to 70? t able 4c. d ifferential dc c haracteristics , v dd = 3.3v?%, t a = 0? to 70? t able 4b. lvcmos/lvttl dc c haracteristics , v dd = 3.3v?%, t a = 0? to 70? symbol parameter test conditions minimum typical maximum units v dd positive supply voltage 3.135 3.3 3.465 v i dd static power supply current r l = 100 135 165 ma no load 60 75 ma symbol parameter test conditions minimum typical maximum units i ih input high current clk v in = v dd = 3.465v 150 ? nclk v in = v dd = 3.465v 5 a i il input low current clk v dd = 3.465v, v in = 0v -5 ? nclk v dd = 3.465v, v in = 0v -150 ? v pp peak-to-peak voltage 0.15 1.3 v v cmr common mode input voltage; note 1, 2 gnd + 0.5 v dd - 0.85 v note 1: for single ended applications, the maximum input voltage for clk, nclk is v dd + 0.3v. note 2: common mode voltage is de ned ast v ih . symbol parameter test conditions minimum typical maximum units v ih input high voltage oe1, oe2 2 v dd + 0.3 v v il input low voltage oe1, oe2 -0.3 0.8 v i ih input high current oe1, oe2 v dd = v in = 3.465v 5 a i il input low current oe1, oe2 v dd = 3.465v, v in = 0v -150 ? a bsolute m aximum r atings supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5 v outputs, v o -0.5v to v dd + 0.5v package thermal impedance, ja 47.9?/w (0 lfpm) storage temperature, t stg -65? to 150? note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress speci cations only. functional operation of product at these conditions or any conditions beyond those listed in the dc characteristics or ac charac- teristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability.
revision b 6/11/15 8516 data sheet 5 low skew, 1-to-16 differential-to-lvds clock distribution chip t able 5. ac c haracteristics , v dd = 3.3v?%, t a = 0? to 70? t able 4d. lvds dc c haracteristics , v dd = 3.3v?%, t a = 0? to 70? symbol parameter test conditions minimum typical maximum units v od differential output voltage 250 400 600 mv v od v od magnitude change 50 mv v os offset voltage 1.125 1.4 1.6 v v os v os magnitude change 50 mv i oz high impedance leakage current -10 +10 ? i off power off leakage -1 +1 ? i osd differential output short circuit current -5.5 ma i os /i osb output short circuit current -12 ma symbol parameter test conditions minimum typical maximum units f max output frequency 700 mhz t pd propagation delay; note 1 1.6 2.0 2.4 ns t sk(o) output skew; note 2, 4 90 ps t sk(pp) part-to-part skew; note 3, 4 500 ps t jit buffer additive phase jitter, rms; refer to additive phase jitter section integration range: 12khz - 20mhz 148 fs t r /t f output rise/fall time 20% to 80% 100 550 ps odc output duty cycle 45 50 55 % t pzl , t pzh output enable time; note 5 5 ns t plz , t phz output disable time; note 5 5 ns note 1: measured from the differential input crossing point to the differential output crossing point. note 2: de ned as skew between outputs at the same supply voltages and with equal load conditions. measured at the output differential cross points. note 3: de ned as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. using the same type of inputs on each device, the outputs are measured at the differential cross points. note 4: this parameter is de ned in accordance with jedec standard 65. note 5: these parameters are guaranteed by characterization. not tested in production.
low skew, 1-to-16 differential-to-lvds clock distribution chip 8516 data sheet 6 revision b 6/11/15 a dditive p hase j itter additive phase jitter @ 155.52mhz (12khz to 20mhz) = 148fs typical -50 -60 -70 -80 -90 -100 -100 -120 -130 -140 -150 -160 1k 10k 100k 1m 10m 100m the spectral purity in a band at a speci c offset from the fundamental compared to the power of the fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the speci ed plot in many applications. phase noise is de ned as the ratio of the noise power present in a 1hz band at a speci ed offset from the fundamental frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in as with most timing speci cations, phase noise measurements have issues. the primary issue relates to the limitations of the equipment. often the noise oor of the equipment is higher than the noise oor of the device. this is illustrated above. the the 1hz band to the power in the fundamental. when the required offset is speci ed, the phase noise is called a dbc value, which simply means dbm at a speci ed offset from the fundamental. by investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. it is mathematically possible to calculate an expected bit error rate given a phase noise plot. device meets the noise oor of what is shown, but can actually be lower. the phase noise is dependant on the input source and measurement equipment. o ffset f rom c arrier f requency (h z ) ssb p hase n oise dbc/h z
revision b 6/11/15 8516 data sheet 7 low skew, 1-to-16 differential-to-lvds clock distribution chip p arameter m easurement i nformation p art - to -p art s kew p ropagation d elay o utput r ise /f all t ime d ifferential i nput l evel o utput s kew 3.3v o utput l oad ac t est c ircuit
low skew, 1-to-16 differential-to-lvds clock distribution chip 8516 data sheet 8 revision b 6/11/15 o utput d uty c ycle /p ulse w idth /p eriod o ffset v oltage s etup p ower o ff l eakage s etup d ifferential o utput s hort circuit c urrent s etup o utput s hort c ircuit c urrent s etup d ifferential o utput v oltage s etup
revision b 6/11/15 8516 data sheet 9 low skew, 1-to-16 differential-to-lvds clock distribution chip a pplication i nformation figure 1 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref = v dd /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to the input pin. the ratio f igure 1. s ingle e nded s ignal d riving d ifferential i nput w iring the d ifferential i nput to a ccept s ingle e nded l evels of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. for example, if the input clock swing is only 2.5v and v dd = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609. i nputs : lvcmos c ontrol p ins : all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k resistor can be used. r ecommendations for u nused i nput and o utput p ins o utputs : lvds ? like o utput all unused lvds output pairs can be either left oating or terminated with 100 across. if they are left oating, we recommend that there is no trace attached.
low skew, 1-to-16 differential-to-lvds clock distribution chip 8516 data sheet 10 revision b 6/11/15 f igure 2c. h i p er c lock s clk/nclk i nput d riven by 3.3v lvpecl d river f igure 2b. h i p er c lock s clk/nclk i nput d riven by 3.3v lvpecl d river f igure 2d. h i p er c lock s clk/nclk i nput d riven by 3.3v lvds d river 3.3v r1 50 r3 50 zo = 50 ohm lvpecl zo = 50 ohm hiperclocks clk nclk 3.3v input r2 50 zo = 50 ohm input hiperclocks clk nclk 3.3v r3 125 r2 84 zo = 50 ohm 3.3v r4 125 lvpecl r1 84 3.3v d ifferential c lock i nput i nterface the clk /nclk accepts lvds, lvpecl, lvhstl, sstl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 2a to 2e show inter- face examples for the hiperclocks clk/nclk input driven by the most common driver types. the input interfaces suggested f igure 2a. h i p er c lock s clk/nclk i nput d riven by ics h i p er c lock s lvhstl d river here are examples only. please consult with the vendor of the driver component to con rm the driver termination requirements. for example in figure 2a, the input termination applies for ics hiperclocks lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. 1.8v r2 50 input lvhstl driver ics hiperclocks r1 50 lvhstl 3.3v zo = 50 ohm zo = 50 ohm hiperclocks clk nclk f igure 2e. h i p er c lock s clk/ n clk i nput d riven by 3.3v lvpecl d river with ac c ouple zo = 50 ohm r3 125 hiperclocks clk nclk 3.3v r5 100 - 200 3.3v r2 84 3.3v r6 100 - 200 input r5,r6 locate near the driver pin. zo = 50 ohm r1 84 r4 125 c2 lvpecl c1 zo = 50 ohm r1 100 3.3v lvds_driv er zo = 50 ohm receiv er clk nclk 3.3v
revision b 6/11/15 8516 data sheet 11 low skew, 1-to-16 differential-to-lvds clock distribution chip lvds d river t ermination a general lvds interface is shown in figure 3. in a 100 differential transmission line environment, lvds drivers require a matched load termination of 100 across near the receiver input. for a multiple lvds outputs buffer, if only partial outputs are used, it is recommended to terminate the un-used outputs. f igure 3. t ypical lvds d river t ermination 3.3v r1 100 zo = 50 ohm lvds_driver hiperclocks clk nclk zo = 50 ohm 3.3v f igure 4. ICS8516 lvds b uffer s chematic e xample c5 0.1u (u1-12) zo = 50 ohm zo = 50 ohm (u1-25) lvds_input + - (u1-31) zo = 50 ohm c3 0.1u c6 0.1u u1 8516 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 36 35 34 33 32 31 30 29 28 27 26 25 48 47 46 45 44 43 42 41 40 39 38 37 vdd nq5 q5 nq4 q4 vdd gnd nq3 q3 nq2 q2 vdd nq1 q1 nq0 q0 gnd nclk clk gnd q15 nq15 q14 nq14 vdd nq10 q10 nq11 q11 vdd gnd nq12 q12 nq13 q13 vdd q6 nq6 q7 nq7 gnd oe1 oe2 gnd nq8 q8 nq9 q9 zo = 50 ohm r16 100 zo = 50 ohm vdd=3.3v lvds_input + - zo = 50 ohm zo = 50 ohm zo = 50 ohm vdd=3.3v r10 100 c4 0.1u c2 0.1u lvds_driver r17 100 lvds_input + - (u1-1) decoupling capacitors located near the power pins (u1-6) (u1-36) r1 100 c1 0.1u s chematic e xample figure 4 shows a schematic example of ICS8516. in this example, the input is driven by an lvds driver. for lvds buffer, it is recommended to terminate the unused outputs for better signal integrity. the decoupling capacitors should be physically located near the power pin.
low skew, 1-to-16 differential-to-lvds clock distribution chip 8516 data sheet 12 revision b 6/11/15 r eliability i nformation t ransistor c ount the transistor count for ICS8516 is: 1821 t able 6. ja vs . a ir f low t able for 48 l ead lqfp ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 67.8?/w 55.9?/w 50.1?/w multi-layer pcb, jedec standard test boards 47.9?/w 42.1?/w 39.4?/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
revision b 6/11/15 8516 data sheet 13 low skew, 1-to-16 differential-to-lvds clock distribution chip t able 7. p ackage d imensions jedec variation all dimensions in millimeters symbol bbc minimum nominal maximum n 48 a -- -- 1.60 a1 0.05 -- 0.15 a2 1.35 1.40 1.45 b 0.17 0.22 0.27 c 0.09 -- 0.20 d 9.00 basic d1 7.00 basic d2 5.50 ref. e 9.00 basic e1 7.00 basic e2 5.50 ref. e 0.50 basic l 0.45 0.60 0.75 0 -- 7 ccc -- -- 0.08 reference document: jedec publication 95, ms-026 p ackage o utline - y s uffix for 48 l ead lqfp
low skew, 1-to-16 differential-to-lvds clock distribution chip 8516 data sheet 14 revision b 6/11/15 t able 8. o rdering i nformation part/order number marking package shipping packaging temperature ICS8516fylf ICS8516fylf 48 lead ?ead-free lqfp tray 0? to 70? ICS8516fylft ICS8516fylf 48 lead ?ead-free lqfp tape & reel 0? to 70? note: parts that are ordered with an ?f suf x to the part number are the pb-free con guration and are rohs compliant.
revision b 6/11/15 8516 data sheet 15 low skew, 1-to-16 differential-to-lvds clock distribution chip revision history sheet rev table page description of change date a t1 2 8 pin description table - added pins 47 thru 48. added lvds driver termination in the application information section. 3/31/03 a t1 2 pin description table - switched pin names for 45, 46 & 47,48 5/6/03 a t2 t8 3 9 12 pin characteristics table - changed c in from 4pf max. to 4pf typical. updated differential clock input interface section. ordering information table - added lead-free part numbers. 7/30/04 b t5 1 5 6 9 feature section - added additive phase jitter bullet. ac characteristics table - added additive phase jitter. added additive phase jitter section. added recommendations for unused input and output pins 2/21/06 bt8 1 17 features section - removed reference to leaded devices. ordering information - removed leaded devices. updated data sheet format. 6/12/15
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